As demands for greater circuit integration have increased, it has become more desirable to decrease the overall area occupied by a semiconductor device. For example, by decreasing the area that a MOS device occupies, the packing density (or number of devices per unit substrate) of the integrated circuit can be increased, thus substantially decreasing chip manufacturing costs.
One significant problem that has been encountered in decreasing the area of a MOS device has been decreasing the area occupied by the source and drain. For example, a conventional MOS device 10 is shown in FIG. 1. An oxide film 15 and a polysilicon film 16 are formed over a P-type semiconductor substrate 20. These films are then patterned to form a gate oxide film 15 and gate 16. Using the gate 16 as a mask, n type impurity ions are implanted in a low concentration in the substrate to form Lightly Doped source/drain (LDD) regions 13. An oxide film is then deposited over the entire exposed surface of the substrate 20 and then subjected to an anisotropic etching to form side wall spacers 17. Finally, n type impurity ions are implanted in a high concentration in the substrate 20 using the side wall spacers 17 as a mask, thereby forming a high concentration source/drain region 14. A channel 19 is defined between the conductivity areas 13, 14 beneath the gate 16.
The isolation space in a semiconductor is the space between adjacent semiconductor devices on the same substrate. Adjacent devices on a substrate are usually separated by a field oxide (FOX) insulator 18. With smaller source/drain regions, adjacent devices may be placed closer together, thus increasing packing density. In order to reduce the overall area occupied by the typical NMOS device of FIG. 1, it would be advantageous to reduce both the source/drain isolation space and the source/drain area.
However, there are several significant limitations to how small the source and drain can be made. Simply reducing the size of the source/drain regions cannot be accomplished while using the MOS fabrication process discussed above. For example, when forming the gate, the gate should be properly aligned between the source and drain regions. If the gate does not extend to the source and drain regions, an incomplete channel will be formed and the device will not work. One method of overcoming this is to form the gate such that it overlaps the source and drain. This overlap should be sufficient to allow for mask registration tolerances and variation in lateral diffusion in the source and drain diffusion step. However, due to this overlap, a stray parasitic capacitance may develop between the gate and source and the gate and drain. To avoid this, the gate may be self-aligned. One method of accomplishing self-alignment is to use ion implantation or diffusion to align the source and drain with the edges of the gate. In this process, the gate and sidewalls are used as a mask for the Lightly Doped Drain (LDD). Subsequently, windows in the photoresist layer are opened with a stepper device. Ions are then diffused or implanted through these windows.
Several factors in this process limit the extent to which the dimensions of the heavily doped source and drains can be reduced. Foremost, the source and drain are limited to be at least on the order of the resolution of the stepper device used to open the windows in the photoresist. Therefore, even if the isolation space for the source/drain regions could be reduced, the width of the source/drain itself cannot be reduced further. Because this is a substantial limitation on the ultimate reduction of the size of the chip, a need exists for a process for reducing the overall area occupied by the source/drain regions, and/or for reducing the isolation space required by the source/drain regions.